1. Field of the Invention
The present invention relates to a MIS semiconductor device which is formed by utilizing a so-called SOI (silicon on insulator) substrate having a semiconductor thin film formed on a substrate through an insulating layer and forming a MIS structure semiconductor element on the semiconductor thin film.
2. Description of the Prior Art
Recently, many advantages have been reported with respect to a so-called thin-film SOI element utilizing an SOI substrate. This element has advantages, for example, of having a high freedom in setting an impurity concentration in a channel region, having a high durability against the .alpha. ray, requiring no latchup, enabling a high speed operation by virtue of a decrease of parasitic capacitance between the substrate and a silicon thin film constituting an element forming region and so on.
For this reason, research and development on the thin film SOI element are extensively being progressed. A MIS field effect transistor (hereinafter simply referred to as "MISFET") utilizing the SOI substrate, by way of example, employs an SOI substrate 4 formed with an insular silicon thin film (so-called SOI film) 3 through an SiO.sub.2 layer 2 on a silicon substrate 1, for example, by adhesion or the like, forms a first conductivity type source region 5, a drain region 6 in the silicon thin film 3, and a gate electrode 8 made of a polycrystalline silicon on the silicon thin film 3 between the source region 5 and the drain region 6 through a gate insulating film 7 made, for example, of SiO.sub.2 or the like as shown in FIG. 1. In FIG. 1, reference numeral 9 designates a source electrode and 10 a drain electrode.
A MISFET 11 utilizing the SOI substrate 4 shown in FIG. 1, however, has a defect that the source-drain breakdown voltage, that is, a tolerance against voltage between the source and the drain is low. This defect is caused in a manner that, as shown in FIG. 1, the minority carrier (electron) e injected into a channel region 12 from the source region 5 flows toward the drain region 6 in the MISFET 11, this electron e gives rise to impact ionization in a high electric field region 13 produced at the end of the drain beneath the gate electrode 8, electron-hole pairs are consequently generated, and the positive hole h thereof flows into the channel region 12. That is, in an ordinary bulk-type MISFET, the positive hole h flowing into the channel region (so-called hole current I.sub.p) is released through the substrate as a substrate current, whereas the SOI substrate is constructed in a manner that the silicon thin film 3 is surrounded by the SiO.sub.2 layer 2 which prevents the positive hole h from being released, so that the above positive hole h is accumulated in the channel region 12 in the vicinity of the source region 5. The accumulated positive hole h gives rise to reducing the height of the energy barrier between the source and the channel, whereby the source acts as the emitter for the electron to generate an electron current I.sub.n, by the bipolar operation, in addition to the normal electron flowing (channel current I.sub.o) through the channel region 12. This electron current I.sub.n leads to a positive feedback phenomenon, wherein the hole current I.sub.p is again generated in the high electric field region 13, to thereby suddenly increase a drain current I.sub.p, which results in decreasing the breakdown voltage between the source and the drain.
There have conventionally been proposed a variety of methods for suppressing the degradation of the breakdown voltage between the source and the drain caused by the impact ionization.
For example, an MISFET 14 shown in FIG. 2 provides a larger thickness at a portion of a silicon film 3 corresponding to a drain region 6 to decrease the electric field at the end of the drain, thereby reducing the occurrence of a hole current due to the impact ionization and improving the breakdown voltage between the source and the drain. However, this method is inconvenient in that the structure is complicated and difficult to manufacture, and sufficient effects cannot be produced. An MISFET 15 shown in FIG. 3, on the other hand, forms a source region 5 and a drain region 6 thinner than the thickness of a silicon thin film 3, a semiconductor region 16 in the same conductivity type as the channel region 12 outside the source region 5 and separated from the source region 5, and an electrode 17 led from the semiconductor region, thereby releasing the positive hole h produced by the impact ionization through the semiconductor region 17 to improve the breakdown voltage between the source and the drain. Since this method requires a large area of the silicon thin film 3 for forming the semiconductor region 16, a parasitic capacitance between the region 12 on the substrate and the drain region 12 is increased, thereby losing an advantage of the MISFET utilizing the SOI substrate. Further, the thickness of the silicon thin film 3 is substantially increased so that a short channel effect is readily produced. For preventing the short channel effect, it is necessary to make the channel concentration higher, which results in losing an advantage of the MISFET utilizing the SOI substrate that the carrier mobility can be enhanced.
Further, a MIS constructed as shown in FIG. 4 has been proposed, regarded as being rational from the viewpoint of the manufacturing process and the structure. In the MISFET 18 shown in FIG. 4, a semiconductor region 16 of the same conductivity type as a channel region 12 is formed outside and adjacent to a shallow source region 5, and a source electrode 9 is used in common, thereby making it possible to use the MISFET as an ordinary three-terminal element. The MISFET 18 can also release the positive hole h produced by the impact ionization through the semiconductor region 16 and the source electrode 9 to improve the drain breakdown voltage. However, if a semiconductor region 19 of the same conductivity type as the semiconductor region 16 is also formed outside a drain region 6 in consideration of a symmetric element structure of the MISFET 18, as shown in FIG. 5, the positive holes h oozing from the semiconductor region 19 to the channel region 12 flows into the semiconductor region 16 on the side of the source region 5 (indicated by a hole current I.sub.p in FIG. 5), which causes an inconvenience of shortcircuiting and consequently conducting between the source and the drain, for example, in a non-operative condition. It is therefore impossible to apply this structure to a switching element such as an access transistor for a static RAM (random access memory) cell which properly uses the source and the drain alternately, whereby an applicable range is limited as a circuit element.